In may copending patent application entitled "Space Charge Current Limited Shunt in a Cascode Circuit for HVTFT Devices" filed concurrently herewith identified by application Ser. No. 565,767, now U.S. Pat. No. 5,073,723, and assigned to the same assignee, I have described an improved printing circuit for high speed and high voltage applications which incorporates my novel leaky low voltage thin film transistor. In that application it is suggested that the cascode circuit of that invention be incorporated into the electrographic writing head 10 schematically illustrated in FIG. 1.
Such a writing head, manufacturable by thin fabrication techniques, is fully disclosed in U.S. Pat. No. 4,588,997. The writing head 10 comprises a linear array of several thousand styli 12 for generating sequential raster lines of information by means of high voltage electrical discharges across a minute air gap to a conductive electrode. In order to drive selected styli in the array, a multiplexing scheme is used wherein the charge on each stylus is controlled by a low voltage thin film pass transistor 14 which selectively charges and discharges the gate of a thin film high voltage transistor 16 for latching the HVTFT. This scheme allows each stylus to maintain its imposed charge, for substantially a line time, between charges and discharges. The drain electrode 18 of HVTFT 16 is connected to high voltage bus 20 (maintained at about 450 volts relative to ground) via load resistor 22, and its source electrode 24 is connected to ground bus 26. Data signals, from data lines 28, on the order of 20 volts (ON) and 0 volts (OFF) will be imposed upon the gate electrode of the HVTFT when the address line 30 switches the gate of LVTFT 14 between about 24 volts (ON) and 0 volts (OFF) during a "gate time" of about 15 to 25 .mu.sec, i.e. the time it takes for the gate of the HVTFT to reach its desired potential.
Writing takes place in electrography when the potential difference between the stylus 12 and a biased complementary electrode (not shown) is sufficient to break down the air gap therebetween. In one form of this art, the complementary electrode is biased to a potential of several hundred volts. In the ON state of the HVTFT 16 writing will take place because the stylus will achieve a low potential so that the difference between it and the complementary electrode is high enough to cause air gap breakdown. When the HVTFT is ON, a current path exists from the high voltage bus 20 to ground through the HVTFT, and the large voltage drop across the load resistor 22 will cause the potential on the stylus 12 to approach ground (typically about 10 volts). In the OFF state of the HVTFT no writing will occur because no current path exists from the high voltage bus to ground, there will be no potential drop across the load resistor, and a high potential (of about 450 volts) will be applied to the stylus 12.
A switching problem arises with this circuit because of the parasitic capacitance between the drain electrode 18 and the gate electrode 32 of the HVTFT induced by the rapid switching of the LVTFT during a gate time. In attempting to turn OFF the HVTFT, its parasitic capacitance tends to raise the voltage of its gate electrode and starts to switch it ON. The result is that the drain electrode (and the stylus) will achieve about 200 to 250 volts rather than the intended 450 volts because the HVTFT doesn't turn fully OFF. Therefore, the stylus will write gray rather than white (non-write).
As set forth in my copending application, a known solution to the switching efficiency problem caused by gate-to-drain parasitic capacitance is the use of a cascode circuit wherein the switching transistor is connected in series with the switched transistor and the gate of the switched transistor is biased to a fixed potential. However, when this solution is applied to an amorphous silicon HVTFT (switched transistor) it triggers an instability in the device which shifts the I.sub.DS vs. V.sub.DS characteristic curve to the right over time. This instability is characterized by a parameter V.sub.X, and the resulting curve is said to be V.sub.X shifted. In FIG. 3, curve A represents an initial (unstressed) condition and curve B represents a V.sub.X shifted condition. This phenomenon occurs when the gate to source voltage (V.sub.GS) is much below threshold (V.sub.TH), as would be the case with a hard OFF condition (see FIG. 4). As a consequence, the output low voltage of the HVTFT (note loadline C based upon a pullup resistor 22 of 450 Meg3/8 crossing the characteristic curves A and B) increases with time (from about 8 volts to about 80 volts), preventing its switching over the entire 450 volt range, and therefore, in the ON state writing gray rather than white. This phenomenon is discussed in copending patent application U.S. Ser. No. 07/366,822 (Yap) filed on June 15, 1989, hereby fully incorporated by reference. The problem is exacerbated as the differential between the OFF state gate voltage and the threshold voltage increases, and no instability occurs at gate voltages just below the threshold of the HVTFT (in the range form about 0.5 to 1 volt). It is the normally higher OFF state leakage current of the HVTFT than the switching LVTFT which gives rise to this problem.
It is the primary object of the present invention to provide a leaky thin film LVTFT having a shunt path through which space charge limited current flows.